![]() Types of Design RulesScalable Design Rules (e.g. Parasitics are generally not specified in unitsĭesign RulesTypical rules:Minumum sizeMinimum spacingAlignment / overlapCompositionNegative features MOSIS SCMOS design rulesDesigned to scale across a wide range of technologies.Designed to support multiple vendors.Designed for educational use.Ergo, fairly conservative.Īnd design rules is the size of a minimum feature.Specifying particularizes the scalable rules. ![]() Via problemsVia may not be cut all the way through.Undesize via has too much resistance.Via may be too large and create short. Oxide problemsVariations in height.Lack of planarity -> step tal 1metal 2metal 2 Wiring problemsDiffusion: changes in doping -> variations in resistance, capacitance.Poly, metal: variations in height, width -> variations in resistance, capacitance.Shorts and opens: Transistor problemsVaraiations in threshold voltage:oxide thickness ion implanatation poly variations.Changes in source/drain diffusion overlap.Variations in substrate. Manufacturing problemsPhotoresist shrinkage, tearing.Variations in material deposition.Variations in temperature.Variations in oxide between lots.Variations across a wafer. Why we need design rulesMasks are tooling for manufacturing.Manufacturing processes have inherent limitations in accuracy.Design rules specify geometry of masks which will provide reasonable yields.Design rules are determined by experience. Layer Interaction in MagicTransistors - where poly, diffusion crosspoly crosses ndiffusion - ntransistorpoly crosses pdiffusion - ptransistorVias - where layers connectMetal 1 connecting to Poly - polycontactMetal 1 connecting to P-Diffusion (normal) - pdcMetal 1 connecting to P-Diffusion (substrate contact) - pscMetal 1 connecting to N-Diffusion (normal) - ndcMetal 1 connecting to N-Diffusion (substrate contact) - nscMetal 1 connecting to Metal 2 - via Magic User-InterfaceGraphic Display WindowCursorBox - specifies area to paintCommand window (not shown)accepts text commands :paint poly :paint red :paint ndiff :paint green :writeprints error & status messages Mask Layers in MagicPoly (red)N Diffusion (green)P Diffusion (brown)Metal (blue)Metal 2 (purple)Well (cross-hatching)Contacts (X) to physical layer)Poly (red) - polysilicon (equivalent to physical layer)ndiff (green) - n diffusion (combination of active, nselect)ntranistor (green/red crosshatch) - combined poly, ndiffpdiff (brown) - p diffusion (combination of active, pselect)ptransistor (brown/red crosshatch) - combined poly, pdiffcontacts: combine layers, cut maskĪbout MagicScalable Grid for Scalable Design RulesGrid distance: l (lambda)Value is process-dependent: l = 0.5 X minimum transistor lengthPainting metaphorPaint squares on grid for each mask layerLayers to interact to form components (e.g. Symbolic Mask LayersKey idea: Reduce layers to those that describe designGenerate physical layers as neededMagic Layout Editor: "Abstract Layersmetal1 (blue) - 1st layer metal (equiv. Mask GenerationMask Design using Layout Editoruser specifies layout objects on different layersoutput: layout filePattern GeneratorReads layout fileGenerates enlarged master image of each mask layerImage printed on glassStep & repeat cameraReduces & copies image onto maskOne copy for each die on waferNote importance of mask alignment Review - CMOS Mask LayersDetermine placement of layout objectsColor coding specifies layersLayout objects:RectanglesPolygonsArbitrary shapesGrid typesAbsolute (micron)Scaleable (lambda) ![]() Roadmap for the term: major topicsVLSI OverviewCMOS Processing & FabricationComponents: Transistors, Wires, & ParasiticsDesign Rules & LayoutCombinational Circuit Design & LayoutSequential Circuit Design & LayoutStandard-Cell Design with CAD ToolsSystems Design using Verilog HDLDesign Project: Complete Chip Without those lectures, this slide cant be finished. However, Id like to thank all professors who create such a good work on those lecture notes. ![]() I cant remember where those slide come from. Lecture 4 Design Rules,Layout and Stick DiagramPradondet of Computer EngineeringKasetsart UniversityĪcknowledgementThis lecture note has been summarized from lecture note on Introduction to VLSI Design, VLSI Circuit Design all over the world.
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